LLVM Weekly - #556, August 26th 2024
Welcome to the five hundred and fifty-sixth issue of LLVM Weekly, a weekly newsletter (published every Monday) covering developments in LLVM, Clang, and related projects. LLVM Weekly is brought to you by Alex Bradbury. Subscribe to future issues at http://llvmweekly.org and pass it on to anyone else you think may be interested. Please send any tips or feedback to asb@asbradbury.org, @llvmweekly or @asbradbury on Twitter, or @llvmweekly@fosstodon.org or @asb@fosstodon.org.
News and articles from around the web and events
According to the LLVM calendar in the coming week there will be the following:
- Office hours with the following hosts: Kristof Beyls, Johannes Doerfert, Amara Emerson.
- Online sync-ups on the following topics: Pointer authentication, SPIR-V, new contributors, OpenMP, Flang, RISC-V, LLVM’s libc, MLIR.
- For more details see the LLVM calendar, getting involved documentation on online sync ups and office hours.
On the forums
LLVM 19.1.0-rc3 was released.
Andrew Savonichev proposed a new tool similar to llvm-reduce that works on DWARF object files.
Brandon Wu shared an RFC on a proposed pass to optimise RISC-V vector register spill.
Hongyu Chen, Daniel Thornburgh, and Prabhu Karthikeyan Rajasekaran proposed improvements to linker script handling in LLD.
Peter Chou started an RFC thread on adding a templating language to clang-doc.
Bill Wendling posted an RFC on adding a
__builtin_get_counted_by
builtin to Clang.Michael Kruse proposes to use LLVM_ENABLE_RUNTIMES for Flang’s runtime.
LLVM commits
The CPU definition was added for the Hazard3 RISC-V core used in the Raspberry Pi RP2350. 9fa2386.
A SME peephole optimiser pass was added for AArch64. 6c189ea.
Errata workaround passes were added to the SPARC backend for the Gaisler GR712RC and UT700 cores. 7faf1a0.
Vector and vector crypto were added to the RISC-V SiFive P400 scheduler model. 7efa068.
CycleAnalysis gained methods to verify cycles and their nesting. b432afc.
The C API was extended with support for creating instructions with custom synchronisation scopes. eb7d535.
An
elect.sync
intrinsic was added for NVPTX. d5e9691.Some of the complexity-based canonicalisation was removed from InstCombine on the basis that it’s unreliable / difficult to reason about. a105877.
SPIR-V learned to sort basic blocks as required by the SPIR-V spec. 0c07e7c.
Lowering of Mul/Div/Shift operations was implemented for the Xtensa backend. fab515c.
A new RISC-V peephole was added to reduce VLs based on demanded VL. 26a8a85.
Clang commits
Support for the “RealtimeSanitizer” was added. RTSan can be used to detect real-time violations e.g. calls to methods that aren’t safe for use in functions with deterministic runtime requirements. d010ec6.
-msmall-data-limit
was defaulted to 0. Users of GP relaxation are encouraged to specify the customisation options explicitly. d3864d9.-ffp-model=aggressive
was introduced andffp-model=fast
was made more limited in effect. 27e5f50.Support for
-fsanitizer-undefined-ignore-overflow-pattern
was added, which disables instrumentation around specific common patterns. 295fe0b.