LLVM Weekly - #376, March 15th 2021

Welcome to the three hundred and seventy-sixth issue of LLVM Weekly, a weekly newsletter (published every Monday) covering developments in LLVM, Clang, and related projects. LLVM Weekly is brought to you by Alex Bradbury. Subscribe to future issues at https://llvmweekly.org and pass it on to anyone else you think may be interested. Please send any tips or feedback to asb@asbradbury.org, or @llvmweekly or @asbradbury on Twitter.

News and articles from around the web

LLVM was accepted as a mentor organisation in Google Summer of Code 2021. Find out more about suggested projects here.

Xilinx have open-sourced their LLVM-based Vitis high level synthesis frontend. The code is available on GitHub.

Asher Mancinelli has blogged about parameterizing GTest by both value and type, using recent work to do this for Flang as an example.

On the mailing lists

• Andrei Safronov proposed the Tensilica Xtensa backend for upstreaming. This backend has been written by Espressif Systems.

• Rafael Auler shared an update on rebasing BOLT and plans for upstreaming it. Chris Lattner posted some thoughts on how BOLT could be added to the project (suggesting to start with a bolt/ top-level directory) and noted that LLVM might benefit from more code moving to top-level directories, e.g. Support/ADT and perhaps the MC layer.

• Pavel Labath proposed removing Linux Mips support from LLDB on the basis that it’s untested and unmaintained.

• Vaibhav Yenamandra posted an RFC on extending Clang’s -fdiagnostic-format to emit machine-readable diagnostics, and proposes using the standardised SARIF format.

• Konrad Trifunovic posted a summary of the discussion so far on upstreaming a SPIR-V backend.

• LLVM 12.0.0-rc3 has been tagged.

• In response to query about a proposed GSoC project on distributed lit testing, Sam McCall described a system used at Google involving a custom runner and distributed build system.

• Serge Pavlov shared an RFC on supporting non-default floating point environments on RISC-V.

LLVM commits

• The M68k backend was committed. 5033431, bec7b16, 8dddc15, 5ac19e0, and more.

• Documentation was added for building a Windows Itanium toolchain. c5c6f18.

• An llvm.experimental.vector.splice intrinsic was added. 2750f3ed.

• Code comments were added to the Arm backend explaining the stack frame layout. 8d632ca.

• -Werror=return=type is now set by default when building LLVM. ce94a16.

• Support was added for handling i64 arguments to RISC-V vector intrinsics on RV32. 0c73a50.

• Support for lowering to WLS (While Loop Start) on Arm targets with low overhead loops was improved. fad70c3.

• The frame layout for RISC-V vectors was updated. a9b9c64.

• Support was added for generating DBG_VALUE_LIST and processing it in LiveDebugValues. 5491a86, e2196dd.

Clang commits

• Initial M68k was committed in Clang. 5eb7a58, 5509748.

• Clang gained a new warning for when a function argument is less aligned than a parameter. 7e5cea5.

• A custom TableGen backend was added for RISC-V vector intrinsics. d6a0560.

Other project commits

• MLIR gained a data layout modeling subsystem, allowing size and alignment properties of a type to be queried. 3ba14fa.

• The first set of flang tests have been ported to gtest. 95193ac.

• The scudo allocator now supports memory tagging in the secondary allocator. 3f71ce8.

• A CMake option was added to build LLVM’s libc standalone, without mixing with another libc (for testing - LLVM’s libc isn’t yet complete enough to use this mode as standard). e9e788d.

• The std::movable, std::copyable, std::semiregular, and std::regular concepts were added to libcxx. dc9f385, 8ef69c6, 1543955, 8d4af1b.