LLVM Weekly - #247, September 24th 2018

Welcome to the two hundred and forty-seventh issue of LLVM Weekly, a weekly newsletter (published every Monday) covering developments in LLVM, Clang, and related projects. LLVM Weekly is brought to you by Alex Bradbury. Subscribe to future issues at https://llvmweekly.org and pass it on to anyone else you think may be interested. Please send any tips or feedback to asb@asbradbury.org, or @llvmweekly or @asbradbury on Twitter.

News and articles from around the web

LLVM 7.0.0 has been released. Thanks to all contributors, testers, packers, and reviewers!

The new LLVM Foundation Board of Directors has been announced. As highlighted in the blog post, thanks are due to David Kipping for acting as treasurer over the past 4 years.

Version 1.18 of the TTA-based Co-Design Environment (TCE) has been released. It is "a toolset for design and programming of customized co-processors (typically DSPs) based on the Transport Triggered Architecture (TTA)." The new release adds support for LLVM 7.0, amongst other changes.

On the mailing lists

• Eric Christopher proposes promoting WebAssembly from an 'experimental' to a 'normal' backend. There is broad support for this. A number of respondents suggest it would be worth promoting the RISC-V backend too. As I clarify on the mailing list, I'm intending to propose this in the next few weeks.

• David Spickett has shared an RFC on new Clang target selection options for ARM/AArch64.

• Jonas Devlieghere started an RFC thread on adding support to LLDB for generating 'reproducers'. This should make it much easier to reproduce an issue or crash.

• Alex Bradbury has updated on the implementation status of his RFC on expanding atomic LL/SC loops.

• Reid Kleckner proposes storing basic block order in llvm::Instruction to speed up local dominance computations.

• Nico Weber started a discussion on whether functions returning bool should use true or false for success. The consensus view seems to be that true for success is most logical, although there is plenty of legacy code in LLVM that doesn't (particularly the parsers).

• David Greene wonders if there is interest in a fast BitVector implementation.

• Paul Anderson is looking for feedback on adding support to the Clang Static Analyzer for the 'SARIF' output format.

LLVM commits

• A new PassInstrumentation framework has been committed. This provides common infrastructure to implement pass execution debugging features such as print-before, print-after, opt-bisec, time-passes etc. r342664.

• The AArch64 assembly parser can now handle more complex expressions as valid relocatable operands. r342455.

• The speed of TableGen's -den-dag-isel generator has been further improved. Extra caching of matching predicates saves ~25 secons of a debug build of X86 -gen-dag-isel. r342467.

• The RISC-V backend gained codegen support for i8/i16/i32 atomicrmw using the 'A' (atomics) instruction set extension. This makes use of the atomics lowering strategy proposed in an llvm-dev RFC. r342534.

• Dependency breaking instructions can now be described in TableGen using the STIPredicate TableGen class. r342555.

Clang commits

• Clang's DeclarationName data structure saw various optimisations and refacgorings. This cuts the runtime of parsing Boost by ~0.8%. r342729.

• Clang's code completion gained support for filenames in include directives. r342449.

Other project commits

• LLDB now has documentation on scripted breakpoint resolvers. r342419.

• libcxx gained support for compiling with [[nodiscard]] attributes present in pre-C++2a versions. It may also add [[nodiscard]] to extra functions (users may opt out of this by defining _LIBCPP_DISABLE_NODISCARD_EXT). r342808.

• LLD can now optimize redundant instructions in global access sequences for PPC64. r342602.